1. Field of the Invention
The present invention relates to a complementary metal oxide semiconductor (hereinafter, a CMOS field effect transistor) of a semiconductor device and a method for manufacturing the same and, more particularly, a method for manufacturing the same having improved characteristics, yield and reliability by performing a decoupled plasma nitridation (DPN) process on a gate oxide film of NMOS structures in the cell region and PMOS structures in the peripheral circuit region to form a silicon nitride on the surface of the gate oxide film.
2. Description of the Related Art
Generally, a CMOS device includes PMOS transistors with low power consumption and NMOS transistors capable of high-speed operation formed symmetrically. Although it has a low degree of integration and a complicated manufacturing process, CMOS devices are generally characterized by low power consumption.
FIG. 1 is a plan view illustrating a cell region and a peripheral circuit region of a semiconductor device.
Referring to FIG. 1, in the CMOS device, the threshold voltage of the NMOS in the cell region 100 should be approximately +1V to reduce the off current during operation of the device, and the threshold voltage of the PMOS and NMOS in the peripheral circuit region 200 should be higher than xe2x88x920.5V and lower than +0.5V, to increase the operating speed. A separate mask and excessive ion implantation is required to achievethis result, which complicates the manufacturing process.
The CMOS gate electrode is typically formed of a polysilicon layer having a high melting point as a result of the ease of deposition of the thin film and line pattern, stability against oxidation atmosphere and ease of planarization.
The conventional gate electrode employs n+ polysilicon for both NMOS and PMOS regions. However, a buried channel is formed due to counter doping in the PMOS region, which results in short channel effects and an increase in leakage current.
In an attempt to overcome these disadvantages, a dual gate electrode, which employs n+ polysilicon as a gate electrode in the NMOS region, and p+ polysilicon in the PMOS region, is used to form a surface channel on both NMOS and PMOS regions.
FIG. 2A through 2E are cross sectional views illustrating a method for manufacturing the conventional CMOS, wherein xe2x80x9cAxe2x80x9d indicates a region on which a cell region NMOS is to be formed, xe2x80x9cBxe2x80x9d indicates a region on which a peripheral circuit region PMOS is to be formed, and xe2x80x9cCxe2x80x9d indicates a region on which a peripheral circuit region NMOS is to be formed.
Referring to FIG. 2A, a field oxide 13 defining an active region is formed on a semiconductor substrate 11.
Then, using an ion implantation mask, p-type and n-type impurities are selectively injected into the semiconductor substrate 11, and a drive-in process is performed to form p-well 15 and n-well 17.
Referring to FIG. 2B, a first oxide film 19 is grown on the semiconductor substrate 11 by a thermal oxidation process, and impurity ions for adjusting the threshold voltage are implanted to the resulting structure. Here, the first oxide film 19 prevents generation of surface defects in the semiconductor substrate 11 during the ion implantation of the impurity ions necessary to adjust the threshold voltage.
Referring to FIG. 2C, the first oxide film 19 is removed, and a second oxide film 21 and an undoped polysilicon layer 23 are formed on the resulting structure.
Subsequently, the polysilicon layer 23 on the p-well 15 is doped with n-type impurities such as phosphorous (P) or arsenic (As) ions by performing an ion implantation using an n-well mask (not shown).
Next, the polysilicon layer 23 on the n-well 17 is doped with p-type impurities such as boron (B) or BF2 ions by performing an ion implantation using a p-well mask.
Referring to FIG. 2D, a metal layer 29 is formed on the polysilicon layer 23.
The metal layer 29, the polysilicon layer 23 and the second oxide film 21 are selectively etched by performing a photolithography process using a gate electrode mask, thereby forming a gate oxide of the second oxide film 21 and a gate electrode 31 on the upper side of the p-well 15 and the n-well 17, respectively. Here, the gate electrode 31 comprises a stacked structure of the polysilicon layer 23 and the metal layer 29.
Referring to FIG. 2E, a low con cent ration n-type impurity region 33 is formed in the p-well 15 on both side of the gate electrode 31 by preforming an ion implantation of n-type impurity ions using the n-well mask (not shown) followed by a drive-in process.
Thereafter a low concentration p-type impurity region 35 is formed in the n-well 17 on both sides of the gate electrode 31 by performing an ion implantation of a low concentration of p-type impurity ions using the p-well mask (not shown) followed by a drive-in process.
Then a nitride spacer 37 is formed on a sidewall of the gate electrode 31.
Subsequently, a high concentration n-type impurity region 39 is formed in the p-well 15 on both sides of the gate electrode 31 including the nitride spacer 37 by performing an ion implantation of a high concentration of n-type impurity ions using the n-well mask (not shown) followed by a drive-in process.
Thereafter, a high concentration p-type impurity region 41 is formed in the n-well 17 on both sides of the gate electrode 31 including the nitride spacer 37 by performing an ion implantation with a high concentration p-type impurity ions using the n-well mask (not shown) and the drive-in process.
As described above, since the conventional CMOS device and its manufacturing method involves the formation of the dual polysilicon gate electrode, the device characteristics of the conventional CMOS device are degraded by the following effects.
First, when boron in the gate oxide film region of a p+ polysilicon gate electrode in the PMOS region is not activated, a gate depletion effect of the gate electrode is generated at the CMOS polysilicon gate electrode, decreasing reverse capacitance and increasing threshold voltage.
Second, the phenomenon of the remaining boron ions in the p+ polysilicon gate electrode penetrating the gate oxide film to diffuse into the channel region of the semiconductor substrate, i.e., boron penetration phenomenon occurs. As a result, the flat band voltage and the threshold voltage are varied, and the gate oxide integrity (GOI) characteristics deteriorate.
It is, therefore, an object of the present invention to provide a CMOS device and a method for manufacturing the same, wherein a single gate CMOS with a surface channel is formed by performing a DPN (Decoupled Plasma Nitridation) process on a gate oxide film of a cell region NMOS and a peripheral circuit region PMOS, and forming a silicon nitride film on the surface of the gate oxide film, thereby more easily forming a single gate CMOS with a surface channel without the need for any excessive ion implantation process even when a gate electrode of n+ polysilicon layer is used, which is possible by having the threshold voltage of the cell region NMOS at approximately +0.9V, the threshold voltage of the peripheral circuit region PMOS at approximately xe2x88x920.5V and below, and lastly, the threshold voltage of the peripheral circuit region NMOS at approximately +0.5V and below.
To achieve the above object, there is provided a CMOS of a semiconductor device that includes: a semiconductor substrate including an n-well and p-well in a peripheral circuit region, and a p-well in a cell region; a gate oxide film a disposed on the semiconductor substrate of the n-well in the peripheral circuit region and the p-well in the cell region, the gate oxide film having a surface nitridized by decoupled plasma nitridation process; and a gate electrode formed on the gate oxide film.
Another aspect of the present invention provides a method for manufacturing the CMOS of the semiconductor device, which includes the steps of: forming a gate oxide film on a semiconductor substrate including an n-well and a p-well in a peripheral circuit region, and a p-well in a cell region; performing a decoupled plasma nitridation process to nitridize a surface of the gate oxide film on the n-well of the peripheral circuit region and the p-well of the cell region; and forming a gate electrode on the gate oxide film.
The principle of the present invention lies in the fact that the gate oxide film of the cell region NMOS and the peripheral circuit region PMOS goes through the DPN (Decoupled Plasma Nitridation) process to form a silicon nitride on the surface of the gate oxide film, thereby forming a single gate CMOS with a surface channel. Therefore, even when a gate electrode of n+polysilicon layer is used, it is possible to have a threshold voltage of the cell region NMOS at approximately +0.9V, the threshold voltage of the peripheral circuit region PMOS at approximately xe2x88x920.5V and below, and lastly, the threshold voltage of the peripheral circuit region NMOS at approximately +0.5V and below, without a separate transient ion implantation process.